The present invention relates to a signal noise reduction system, and in particular to a noise reduction system having a main signal path and an auxiliary signal path.
Noise reduction systems have been developed since, at least, the 1960's. Exemplary of these early systems is one developed by Dolby Laboratories in England which was the subject of U.S. Pat. No. 3,361,365. These early systems first incorporated the principles of signal compression and expansion to cancel noise in an input signal. Many conventional noise reduction systems can be characterized by the simple circuit shown in FIG. 1, In this circuit, an input signal including noise is fed through a main signal path and through an auxiliary signal path. The respective outputs of these two paths are summed, or added, in an adding unit which produces a compressed signal output. The compressed signal may subsequently be stored by well-known storage means, not shown in FIG. 1. Upon playback, the stared signal is expanded with the result that the original input signal is reproduced with reduced noise.
The adding unit generally includes a differential amplifying means, wherein the signal present on the auxiliary signal path is added to the signal present on the main signal path which is directly applied to the adding means. The auxiliary signal path typically includes a high-pass filter (HPF) having a variable cutoff frequency, and the signal on the auxiliary signal path is applied to the adding mean through a limiter via the HPF.
This conventional system may be alternately implemented in the circuit shown in FIG. 2. This alternate implementation which uses a voltage to current converter in conjunction with a variable current amplifier to achieve similar results is disclosed, for example, in U .S. Pat. No. 4,547,741 to Katakura.
The desired noise reduction effects of the foregoing circuits are, however, lost, at least in part, when such circuits are implemented in a semiconductor. The manufacturing steps required to produce a semiconductor implementation of the circuit often produce resistors, i e., signal dividing or computing elements, having variable performance characteristics. The resulting impedance mismatch between the signal paths adversely affects the signal outputs and causes overall circuit performance to deteriorate.
The circuit disclosed in Korean application No. 91-9841, and shown for example in FIG. 3, solves this problem by including the signal computing elements within the main signal path, and by including a HPF and voltage buffer in the auxiliary path. As shown in FIG. 3, the auxiliary path is formed separate from the main path such that when a signal from the auxiliary path is electrically combined with the signal on the main path an impedance mismatch between the signal paths is not reflected at the differential amplifier of the adding means and, thus, in the compressed signal output.
Referring to FIG. 3, a signal is input at terminal 1 and directed to adder 5 through main signal path 11. An auxiliary signal path 12 is connected to adder 5, and includes a HPF 13, a voltage buffer 15, and limiter 9. The output of this circuit is apparent at terminal 2.
The main and auxiliary signal paths derive signals using resistor means R.sub.1 and R.sub.2. The resistance of these means should be small to provide sufficient output signal strength. Furthermore, the inherent voltage division which occurs between R.sub.1 and R.sub.2 makes the calculation of these respective resistances an important lay-out consideration during semiconductor design. In addition, voltage buffer 15 is typically implemented using a differential amplifying means which has an internal resistance. Experience has shown that unaccounted for variations in the foregoing resistances, and in particular, unexpected variations in these resistances caused during semiconductor fabrication processes results in unacceptable circuit performance.